1. Field of the Invention
This invention relates generally to a low distortion crystal oscillator and, more particularly, to a crystal oscillator that provides smooth transitions between highs and lows in the output signal of the oscillator so as to eliminate harmonic distortion caused by sharp transitions.
2. Discussion of the Related Art
Most circuits that use digital logic require a clock circuit in order to generate a clocking signal from which the digital logic elements can be controlled. Typically, the clock circuit will include a crystal oscillator having some type of piezoelectric device, such as a quartz crystal or a crystal resonator, in order to generate an oscillation frequency. For most digital logic circuits, the oscillator circuit is generally an integrated circuit that takes advantage of complimentary metal oxide semi-conductor (CMOS) technology. Known crystal oscillators produce square wave output clocking signals having sharp transitions between "highs" and "lows" of the wave. An oscillator of this type is discussed in A. B. Grebene, "Bipolar MOS Analog Integrated Circuit Design," Wiley-Interscience, 1984, pp. 551-555.
FIG. 1 shows a prior art schematic diagram of an oscillator circuit 10 of the type discussed above which can be used to generate a clocking signal. The oscillator circuit 10 includes an equivalent circuit of a piezoelectric resonator, such as a quartz crystal or crystal resonator, represented generally at 12. The resonator circuit 12 is an RCL circuit including a resistor R.sub.1, capacitors C.sub.1 and C.sub.2, and an inductor L.sub.1. An equivalent circuit representation of a crystal oscillator as depicted by the circuit 12 is well known in the art. For a typical crystal resonator having a resonant frequency of 12 MHz, R.sub.1 would be about 5.5 ohms, C.sub.1 would be about 5.1 picofarads (pF), C.sub.2 would be about 34.4 pF, and L.sub.1 would be about 37.5 microHenries (.mu.H). Capacitors C.sub.3 and C.sub.4 are load capacitors which help generate and sustain the oscillation of the resonator circuit 12 as is well understood in the art. For the above resonant frequency of 12 MHz, the load capacitors C.sub.3 and C.sub.4 would have a value of approximately 30 pF.
The oscillator circuit 10 also includes an inverter circuit 14. The inverter circuit 14 includes a P-channel metal oxide semiconductor field effect transistor (MOSFET) 16 and an N-channel MOSFET 18. Each of the FETs 16 and 18 include a source terminal, a gate terminal, and a drain terminal, labelled S, G and D, respectively. Additionally, for each of the FETs 16 and 18, a substrate terminal is shown connected to its source terminal. As is apparent by reviewing the inverter circuit 14, the source terminal of the FET 16 is connected to an input voltage V.sub.cc and the source terminal of the FET 18 connected to ground. Additionally, the gate terminals of the FETs 16 and 18 are connected together and the drain terminals of the FETs 16 and 18 are connected together. The connection point between the gate terminals of the FETs 16 and 18 is an input node 20, and the connection point between the drain terminals of the FETs 16 and 18 is an output node 22 of the inverter circuit 14. As is apparent from FIG. 1, the output node 22 is electrically connected to an input side of the resonator circuit 12, and the input node 20 is electrically connected to an output side of the resonator circuit 12. An output clocking signal from the oscillator circuit 10 is taken from the node 22 and is subsequently applied to digital logic circuitry (not shown) in a manner that is well understood in the art.
The purpose of the inverter circuit 14 is to provide a loop gain that is greater than one in order to initiate and sustain oscillations of the resonator circuit 12. Ideally, the gain of the inverter circuit 14 need only be greater than unity at the resonant frequency. However, due to process and temperature variations, the gain of the inverter circuit 14 is generally set within the range of about 15-20 db in order to guarantee a sustained, stable oscillation. High gains, however, tend to drive up the size of the inverter circuit 14.
A low signal at the node 20 causes the FET 16 to conduct such that current from the voltage source V.sub.cc is applied to the node 22 which in turn causes the resonator circuit 12 to be energized as capacitor C.sub.4 is charged. During a stable, sustained oscillation, the node 20 will then go high which causes the FET 18 to start conducting such that the node 22 will be forced toward ground, and the FET 16 to stop conducting. This will then drive the node 22 low. The nodes 20 and 22 oscillate in this manner in tune with the resonant frequency of the resonator circuit 12. The inverter circuit 14 provides a 180.degree. phase shift and the impedance of the crystal resonator along with the load capacitors C.sub.3 and C.sub.4 provide another 180.degree. phase shift at the resonant frequency of the resonant circuit 12 such that the resonant circuit 12 can maintain the sustained oscillation. The output signal at the node 22 is distorted clocking signal having sharp transitions between V.sub.cc and ground.
One drawback with the above-described oscillator circuit 10 is that there are sharp transitions between a high V.sub.cc signal and a low ground signal at the output node 22. These sharp transitions as a result of the FETs 16 and 18 become conductive and nonconductive produce high distortion from high level harmonics. These high level harmonics are a major source of emitted noise, such as radio frequency interference (RFI) and electromagnetic interference (EMI). This emitted noise can cause interference and failure in electronic systems.
A feedback resistor R.sub.2 is provided between the nodes 20 and 22 in order to provide the necessary impedance and phase shift in the circuit 12 to force the inverter circuit 14 to change states. The purpose of the resistor R.sub.2 is to put the inverter circuit 14 in a high gain position at start-up where the input node 20 and the output node 22 are at substantially the same potential, and both the FETs 16 and 18 are in their saturation regions such that they are conducting. In order to provide this function, the value of the resistor R.sub.2 is set depending on the resonant frequency of the circuit 12. For lower frequency crystals, R.sub.2 is generally greater than 1 megaohm, and for higher frequency crystals, i.e., greater than 1 MHz, the value of R.sub.2 is generally between 500 kohms and 1 megaohm. Once the resonator circuit 12 is oscillating, the resistor R.sub.2 is not needed, but its presence provides some noise immunity to external noise sources received by the circuit 10.
The start-up time at which the quartz crystal or crystal resonator maintains a sustained oscillation is controlled by two factors. First, the resonator circuit 12 sets the Q of the oscillator circuit 10. The start-up time is proportion to the Q value. This factor is, however, fixed for any given crystal and has little variation. The second factor is a combination of the output impedance of the inverter circuit 14, the feedback resistor R.sub.2, the load capacitors C.sub.3 and C.sub.4 and the case capacitance of the crystal. These factors combine to create an RC time constant that directly effects the start-up time. The case capacitance is fixed for a given crystal and the load capacitance cannot be changed without affecting the frequency of oscillation. The start-up time can be minimized by reducing the value of the feedback resistor R.sub.2 or the output impedance of the inverter circuit 14. Reducing the value of the feedback resistor R.sub.2 increases the losses of the inverter circuit 14, and thus, there is limitations on how low the value of the resistor R.sub.2 can be. Reducing R.sub.2 also increases the phase noise of the overall oscillator circuit 10. The output impedance of the inverter circuit 14 can be reduced by making the FETs 16 and 18 larger, but as the size of the inverter circuit 14 is increased, the increase in the gate capacitance of the inverter circuit 14 will overshadow the effects of the lower output impedance, and the start-up time will begin to increase rather than decrease. Therefore, for typical applications, the size of the inverter circuit 14 is generally large, and thus the gain of the inverter circuit 14 is high.
What is needed is an oscillator circuit that provides quick start-up, is reduced in size, and does not emit substantial interfering noise. It is therefore an object of the present invention to provide such an oscillator circuit for producing a clocking signal.